)]}'
{
  "commit": "9a31fa395c19d5873190bf84c8192f5799861342",
  "tree": "d25ec2caaa8170fedaf03cc6a8eaa4bad625ac65",
  "parents": [
    "a34f778cb89a8554a5d1f5a75b297c07c672afce"
  ],
  "author": {
    "name": "Takeshi Kihara",
    "email": "takeshi.kihara.df@renesas.com",
    "time": "Fri Apr 20 21:27:43 2018 +0900"
  },
  "committer": {
    "name": "Geert Uytterhoeven",
    "email": "geert+renesas@glider.be",
    "time": "Tue Apr 24 09:54:34 2018 +0200"
  },
  "message": "clk: renesas: Add r8a77990 CPG Core Clock Definitions\n\nThis patch adds all R-Car E3 Clock Pulse Generator Core Clock Outputs.\n\nNote that internal CPG clocks (S0, S1, S2, S3, SDSRC, POST3) are not\nincluded, as they are used as internal clock sources only, and never\nreferenced from DT.\n\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n[shimoda: add SPDX-License-Identifier]\nSigned-off-by: Yoshihiro Shimoda \u003cyoshihiro.shimoda.uh@renesas.com\u003e\nSigned-off-by: Geert Uytterhoeven \u003cgeert+renesas@glider.be\u003e\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "a596a482f3a9bc10f1b5fc04a96b3902a7ac01d1",
      "new_mode": 33188,
      "new_path": "include/dt-bindings/clock/r8a77990-cpg-mssr.h"
    }
  ]
}