)]}'
{
  "commit": "448bd857d48e69b33ef323739dc6d8ca20d4cda7",
  "tree": "4c1178f9c7dd2d78af2ac1ed26b214b04be1554a",
  "parents": [
    "8497f696686ae1ab3f01e5956046d59844b9f500"
  ],
  "author": {
    "name": "Huang Ying",
    "email": "ying.huang@intel.com",
    "time": "Sat Jun 23 10:23:51 2012 +0800"
  },
  "committer": {
    "name": "Bjorn Helgaas",
    "email": "bhelgaas@google.com",
    "time": "Sat Jun 23 10:50:59 2012 -0600"
  },
  "message": "PCI/PM: add PCIe runtime D3cold support\n\nThis patch adds runtime D3cold support and corresponding ACPI platform\nsupport.  This patch only enables runtime D3cold support; it does not\nenable D3cold support during system suspend/hibernate.\n\nD3cold is the deepest power saving state for a PCIe device, where its main\npower is removed.  While it is in D3cold, you can\u0027t access the device at\nall, not even its configuration space (which is still accessible in D3hot).\nTherefore the PCI PM registers can not be used to transition into/out of\nthe D3cold state; that must be done by platform logic such as ACPI _PR3.\n\nTo support wakeup from D3cold, a system may provide auxiliary power, which\nallows a device to request wakeup using a Beacon or the sideband WAKE#\nsignal.  WAKE# is usually connected to platform logic such as ACPI GPE.\nThis is quite different from other power saving states, where devices\nrequest wakeup via a PME message on the PCIe link.\n\nSome devices, such as those in plug-in slots, have no direct platform\nlogic.  For example, there is usually no ACPI _PR3 for them.  D3cold\nsupport for these devices can be done via the PCIe Downstream Port leading\nto the device.  When the PCIe port is powered on/off, the device is powered\non/off too.  Wakeup events from the device will be notified to the\ncorresponding PCIe port.\n\nFor more information about PCIe D3cold and corresponding ACPI support,\nplease refer to:\n\n- PCI Express Base Specification Revision 2.0\n- Advanced Configuration and Power Interface Specification Revision 5.0\n\n[bhelgaas: changelog]\nReviewed-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nOriginally-by: Zheng Yan \u003czheng.z.yan@intel.com\u003e\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a9efebc586b4712293259fd677c6006e57a9bca5",
      "old_mode": 33188,
      "old_path": "drivers/pci/pci-acpi.c",
      "new_id": "e1658afef873668660dc2589eda17535c8797569",
      "new_mode": 33188,
      "new_path": "drivers/pci/pci-acpi.c"
    },
    {
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      "old_id": "bf0cee629b60f8bb763b4407f631e7ba7e778aa8",
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      "old_path": "drivers/pci/pci-driver.c",
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      "new_mode": 33188,
      "new_path": "drivers/pci/pci-driver.c"
    },
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      "old_mode": 33188,
      "old_path": "drivers/pci/pci-sysfs.c",
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      "new_mode": 33188,
      "new_path": "drivers/pci/pci-sysfs.c"
    },
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      "old_path": "drivers/pci/pci.c",
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      "new_path": "drivers/pci/pci.c"
    },
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      "new_path": "drivers/pci/pci.h"
    },
    {
      "type": "modify",
      "old_id": "7c576b9aa01da142993e1c5dcbe0868b95d219dd",
      "old_mode": 33188,
      "old_path": "drivers/pci/pcie/portdrv_pci.c",
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      "new_mode": 33188,
      "new_path": "drivers/pci/pcie/portdrv_pci.c"
    },
    {
      "type": "modify",
      "old_id": "d8c379dba6adbb36ae9df6c18adea304e2c6b45c",
      "old_mode": 33188,
      "old_path": "include/linux/pci.h",
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      "new_path": "include/linux/pci.h"
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}
