tree 9270fc8f956f199c9b1d6cba8a845525d88c23a4
parent cdc749e22925d5b370cb51ace3cace940bd76cb5
author Biju Das <biju.das@bp.renesas.com> 1522265171 +0100
committer Geert Uytterhoeven <geert+renesas@glider.be> 1523878778 +0200

clk: renesas: Add r8a77470 CPG Core Clock Definitions

Add all RZ/G1C Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2 ("List of Clocks [RZ/G1C]") of the RZ/G1C Hardware User's
Manual.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
[geert: Use consecutive numbering]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>