| /* Copyright Statement: |
| * |
| * This software/firmware and related documentation ("MediaTek Software") are |
| * protected under relevant copyright laws. The information contained herein |
| * is confidential and proprietary to MediaTek Inc. and/or its licensors. |
| * Without the prior written permission of MediaTek inc. and/or its licensors, |
| * any reproduction, modification, use or disclosure of MediaTek Software, |
| * and information contained herein, in whole or in part, shall be strictly prohibited. |
| */ |
| /* MediaTek Inc. (C) 2010. All rights reserved. |
| * |
| * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES |
| * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES |
| * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK |
| * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR |
| * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND |
| * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * The following software/firmware and/or related documentation ("MediaTek Software") |
| * have been modified by MediaTek Inc. All revisions are subject to any receiver's |
| * applicable license agreements with MediaTek Inc. |
| */ |
| |
| #ifndef MT6575_SD_H |
| #define MT6575_SD_H |
| |
| #include <linux/bitops.h> |
| #include <linux/mmc/host.h> |
| |
| // #include <mach/mt6575_reg_base.h> /* --- by chhung */ |
| |
| /*--------------------------------------------------------------------------*/ |
| /* Common Definition */ |
| /*--------------------------------------------------------------------------*/ |
| #define MSDC_FIFO_SZ (128) |
| #define MSDC_FIFO_THD (64) // (128) |
| #define MSDC_NUM (4) |
| |
| #define MSDC_MS (0) |
| #define MSDC_SDMMC (1) |
| |
| #define MSDC_BUS_1BITS (0) |
| #define MSDC_BUS_4BITS (1) |
| #define MSDC_BUS_8BITS (2) |
| |
| #define MSDC_BRUST_8B (3) |
| #define MSDC_BRUST_16B (4) |
| #define MSDC_BRUST_32B (5) |
| #define MSDC_BRUST_64B (6) |
| |
| #define MSDC_PIN_PULL_NONE (0) |
| #define MSDC_PIN_PULL_DOWN (1) |
| #define MSDC_PIN_PULL_UP (2) |
| #define MSDC_PIN_KEEP (3) |
| |
| #define MSDC_MAX_SCLK (48000000) /* +/- by chhung */ |
| #define MSDC_MIN_SCLK (260000) |
| |
| #define MSDC_AUTOCMD12 (0x0001) |
| #define MSDC_AUTOCMD23 (0x0002) |
| #define MSDC_AUTOCMD19 (0x0003) |
| |
| #define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */ |
| #define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */ |
| |
| enum { |
| RESP_NONE = 0, |
| RESP_R1, |
| RESP_R2, |
| RESP_R3, |
| RESP_R4, |
| RESP_R5, |
| RESP_R6, |
| RESP_R7, |
| RESP_R1B |
| }; |
| |
| /*--------------------------------------------------------------------------*/ |
| /* Register Offset */ |
| /*--------------------------------------------------------------------------*/ |
| #define MSDC_CFG (0x0) |
| #define MSDC_IOCON (0x04) |
| #define MSDC_PS (0x08) |
| #define MSDC_INT (0x0c) |
| #define MSDC_INTEN (0x10) |
| #define MSDC_FIFOCS (0x14) |
| #define MSDC_TXDATA (0x18) |
| #define MSDC_RXDATA (0x1c) |
| #define SDC_CFG (0x30) |
| #define SDC_CMD (0x34) |
| #define SDC_ARG (0x38) |
| #define SDC_STS (0x3c) |
| #define SDC_RESP0 (0x40) |
| #define SDC_RESP1 (0x44) |
| #define SDC_RESP2 (0x48) |
| #define SDC_RESP3 (0x4c) |
| #define SDC_BLK_NUM (0x50) |
| #define SDC_CSTS (0x58) |
| #define SDC_CSTS_EN (0x5c) |
| #define SDC_DCRC_STS (0x60) |
| #define EMMC_CFG0 (0x70) |
| #define EMMC_CFG1 (0x74) |
| #define EMMC_STS (0x78) |
| #define EMMC_IOCON (0x7c) |
| #define SDC_ACMD_RESP (0x80) |
| #define SDC_ACMD19_TRG (0x84) |
| #define SDC_ACMD19_STS (0x88) |
| #define MSDC_DMA_SA (0x90) |
| #define MSDC_DMA_CA (0x94) |
| #define MSDC_DMA_CTRL (0x98) |
| #define MSDC_DMA_CFG (0x9c) |
| #define MSDC_DBG_SEL (0xa0) |
| #define MSDC_DBG_OUT (0xa4) |
| #define MSDC_PATCH_BIT (0xb0) |
| #define MSDC_PATCH_BIT0 MSDC_PATCH_BIT |
| #define MSDC_PATCH_BIT1 (0xb4) |
| #define MSDC_PAD_CTL0 (0xe0) |
| #define MSDC_PAD_CTL1 (0xe4) |
| #define MSDC_PAD_CTL2 (0xe8) |
| #define MSDC_PAD_TUNE (0xec) |
| #define MSDC_DAT_RDDLY0 (0xf0) |
| #define MSDC_DAT_RDDLY1 (0xf4) |
| #define MSDC_HW_DBG (0xf8) |
| #define MSDC_VERSION (0x100) |
| #define MSDC_ECO_VER (0x104) |
| |
| /*--------------------------------------------------------------------------*/ |
| /* Register Mask */ |
| /*--------------------------------------------------------------------------*/ |
| |
| /* MSDC_CFG mask */ |
| #define MSDC_CFG_MODE (0x1 << 0) /* RW */ |
| #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ |
| #define MSDC_CFG_RST (0x1 << 2) /* RW */ |
| #define MSDC_CFG_PIO (0x1 << 3) /* RW */ |
| #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ |
| #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ |
| #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ |
| #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ |
| #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ |
| #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ |
| |
| /* MSDC_IOCON mask */ |
| #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ |
| #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ |
| #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ |
| #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ |
| #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ |
| #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ |
| #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ |
| #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ |
| #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ |
| #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ |
| #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ |
| #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ |
| #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ |
| #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ |
| #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ |
| |
| /* MSDC_PS mask */ |
| #define MSDC_PS_CDEN (0x1 << 0) /* RW */ |
| #define MSDC_PS_CDSTS (0x1 << 1) /* R */ |
| #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ |
| #define MSDC_PS_DAT (0xff << 16) /* R */ |
| #define MSDC_PS_CMD (0x1 << 24) /* R */ |
| #define MSDC_PS_WP (0x1UL << 31) /* R */ |
| |
| /* MSDC_INT mask */ |
| #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ |
| #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ |
| #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ |
| #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ |
| #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ |
| #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ |
| #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ |
| #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ |
| #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ |
| #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ |
| #define MSDC_INT_CSTA (0x1 << 11) /* R */ |
| #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ |
| #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ |
| #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ |
| #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ |
| #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ |
| |
| /* MSDC_INTEN mask */ |
| #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ |
| #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ |
| #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ |
| #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ |
| #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ |
| #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ |
| #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ |
| #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ |
| #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ |
| #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ |
| #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ |
| #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ |
| #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ |
| #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ |
| #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ |
| #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ |
| |
| /* MSDC_FIFOCS mask */ |
| #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ |
| #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ |
| #define MSDC_FIFOCS_CLR (0x1UL << 31) /* RW */ |
| |
| /* SDC_CFG mask */ |
| #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ |
| #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ |
| #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ |
| #define SDC_CFG_SDIO (0x1 << 19) /* RW */ |
| #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ |
| #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ |
| #define SDC_CFG_DTOC (0xffUL << 24) /* RW */ |
| |
| /* SDC_CMD mask */ |
| #define SDC_CMD_OPC (0x3f << 0) /* RW */ |
| #define SDC_CMD_BRK (0x1 << 6) /* RW */ |
| #define SDC_CMD_RSPTYP (0x7 << 7) /* RW */ |
| #define SDC_CMD_DTYP (0x3 << 11) /* RW */ |
| #define SDC_CMD_DTYP (0x3 << 11) /* RW */ |
| #define SDC_CMD_RW (0x1 << 13) /* RW */ |
| #define SDC_CMD_STOP (0x1 << 14) /* RW */ |
| #define SDC_CMD_GOIRQ (0x1 << 15) /* RW */ |
| #define SDC_CMD_BLKLEN (0xfff << 16) /* RW */ |
| #define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */ |
| #define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */ |
| |
| /* SDC_STS mask */ |
| #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ |
| #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ |
| #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ |
| |
| /* SDC_DCRC_STS mask */ |
| #define SDC_DCRC_STS_NEG (0xf << 8) /* RO */ |
| #define SDC_DCRC_STS_POS (0xff << 0) /* RO */ |
| |
| /* EMMC_CFG0 mask */ |
| #define EMMC_CFG0_BOOTSTART (0x1 << 0) /* W */ |
| #define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* W */ |
| #define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW */ |
| #define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW */ |
| #define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW */ |
| #define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW */ |
| |
| /* EMMC_CFG1 mask */ |
| #define EMMC_CFG1_BOOTDATTMC (0xfffff << 0) /* RW */ |
| #define EMMC_CFG1_BOOTACKTMC (0xfffUL << 20) /* RW */ |
| |
| /* EMMC_STS mask */ |
| #define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C */ |
| #define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C */ |
| #define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C */ |
| #define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C */ |
| #define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* R */ |
| #define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C */ |
| #define EMMC_STS_BOOTDATRCV (0x1 << 6) /* R */ |
| |
| /* EMMC_IOCON mask */ |
| #define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW */ |
| |
| /* SDC_ACMD19_TRG mask */ |
| #define SDC_ACMD19_TRG_TUNESEL (0xf << 0) /* RW */ |
| |
| /* MSDC_DMA_CTRL mask */ |
| #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ |
| #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ |
| #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ |
| #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ |
| #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ |
| #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ |
| #define MSDC_DMA_CTRL_XFERSZ (0xffffUL << 16)/* RW */ |
| |
| /* MSDC_DMA_CFG mask */ |
| #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ |
| #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ |
| #define MSDC_DMA_CFG_BDCSERR (0x1 << 4) /* R */ |
| #define MSDC_DMA_CFG_GPDCSERR (0x1 << 5) /* R */ |
| |
| /* MSDC_PATCH_BIT mask */ |
| #define MSDC_PATCH_BIT_WFLSMODE (0x1 << 0) /* RW */ |
| #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ |
| #define MSDC_PATCH_BIT_CKGEN_CK (0x1 << 6) /* E2: Fixed to 1 */ |
| #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ |
| #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ |
| #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ |
| #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ |
| #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ |
| #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ |
| #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ |
| #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ |
| #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ |
| |
| /* MSDC_PATCH_BIT1 mask */ |
| #define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 3) |
| #define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 0) |
| |
| /* MSDC_PAD_CTL0 mask */ |
| #define MSDC_PAD_CTL0_CLKDRVN (0x7 << 0) /* RW */ |
| #define MSDC_PAD_CTL0_CLKDRVP (0x7 << 4) /* RW */ |
| #define MSDC_PAD_CTL0_CLKSR (0x1 << 8) /* RW */ |
| #define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */ |
| #define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */ |
| #define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */ |
| #define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */ |
| #define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */ |
| #define MSDC_PAD_CTL0_CLKRDSEL (0xffUL << 24) /* RW */ |
| |
| /* MSDC_PAD_CTL1 mask */ |
| #define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */ |
| #define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */ |
| #define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */ |
| #define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */ |
| #define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */ |
| #define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */ |
| #define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */ |
| #define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */ |
| #define MSDC_PAD_CTL1_CMDRDSEL (0xffUL << 24) /* RW */ |
| |
| /* MSDC_PAD_CTL2 mask */ |
| #define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */ |
| #define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */ |
| #define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */ |
| #define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */ |
| #define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */ |
| #define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */ |
| #define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */ |
| #define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */ |
| #define MSDC_PAD_CTL2_DATRDSEL (0xffUL << 24) /* RW */ |
| |
| /* MSDC_PAD_TUNE mask */ |
| #define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */ |
| #define MSDC_PAD_TUNE_DATRRDLY (0x1F << 8) /* RW */ |
| #define MSDC_PAD_TUNE_CMDRDLY (0x1F << 16) /* RW */ |
| #define MSDC_PAD_TUNE_CMDRRDLY (0x1FUL << 22) /* RW */ |
| #define MSDC_PAD_TUNE_CLKTXDLY (0x1FUL << 27) /* RW */ |
| |
| /* MSDC_DAT_RDDLY0/1 mask */ |
| #define MSDC_DAT_RDDLY0_D0 (0x1F << 0) /* RW */ |
| #define MSDC_DAT_RDDLY0_D1 (0x1F << 8) /* RW */ |
| #define MSDC_DAT_RDDLY0_D2 (0x1F << 16) /* RW */ |
| #define MSDC_DAT_RDDLY0_D3 (0x1F << 24) /* RW */ |
| |
| #define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */ |
| #define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */ |
| #define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */ |
| #define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */ |
| |
| #define MSDC_CKGEN_MSDC_DLY_SEL (0x1F << 10) |
| #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) |
| #define MSDC_CKGEN_MSDC_CK_SEL (0x1 << 6) |
| #define CARD_READY_FOR_DATA BIT(8) |
| #define CARD_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) |
| |
| /*--------------------------------------------------------------------------*/ |
| /* Descriptor Structure */ |
| /*--------------------------------------------------------------------------*/ |
| struct gpd { |
| u32 hwo:1; /* could be changed by hw */ |
| u32 bdp:1; |
| u32 rsv0:6; |
| u32 chksum:8; |
| u32 intr:1; |
| u32 rsv1:15; |
| void *next; |
| void *ptr; |
| u32 buflen:16; |
| u32 extlen:8; |
| u32 rsv2:8; |
| u32 arg; |
| u32 blknum; |
| u32 cmd; |
| }; |
| |
| struct bd { |
| u32 eol:1; |
| u32 rsv0:7; |
| u32 chksum:8; |
| u32 rsv1:1; |
| u32 blkpad:1; |
| u32 dwpad:1; |
| u32 rsv2:13; |
| void *next; |
| void *ptr; |
| u32 buflen:16; |
| u32 rsv3:16; |
| }; |
| |
| struct msdc_dma { |
| struct gpd *gpd; /* pointer to gpd array */ |
| struct bd *bd; /* pointer to bd array */ |
| dma_addr_t gpd_addr; /* the physical address of gpd array */ |
| dma_addr_t bd_addr; /* the physical address of bd array */ |
| }; |
| |
| struct msdc_host { |
| struct msdc_hw *hw; |
| |
| struct mmc_host *mmc; /* mmc structure */ |
| struct mmc_command *cmd; |
| struct mmc_data *data; |
| struct mmc_request *mrq; |
| int cmd_rsp; |
| |
| int error; |
| spinlock_t lock; /* mutex */ |
| struct semaphore sem; |
| |
| u32 blksz; /* host block size */ |
| void __iomem *base; /* host base address */ |
| int id; /* host id */ |
| int pwr_ref; /* core power reference count */ |
| |
| u32 xfer_size; /* total transferred size */ |
| |
| struct msdc_dma dma; /* dma channel */ |
| u32 dma_xfer_size; /* dma transfer size in bytes */ |
| |
| u32 timeout_ns; /* data timeout ns */ |
| u32 timeout_clks; /* data timeout clks */ |
| |
| int irq; /* host interrupt */ |
| |
| struct delayed_work card_delaywork; |
| |
| struct completion cmd_done; |
| struct completion xfer_done; |
| struct pm_message pm_state; |
| |
| u32 mclk; /* mmc subsystem clock */ |
| u32 hclk; /* host clock speed */ |
| u32 sclk; /* SD/MS clock speed */ |
| u8 core_clkon; /* Host core clock on ? */ |
| u8 card_clkon; /* Card clock on ? */ |
| u8 core_power; /* core power */ |
| u8 power_mode; /* host power mode */ |
| u8 card_inserted; /* card inserted ? */ |
| u8 suspend; /* host suspended ? */ |
| u8 app_cmd; /* for app command */ |
| u32 app_cmd_arg; |
| }; |
| |
| static inline void sdr_set_bits(void __iomem *reg, u32 bs) |
| { |
| u32 val = readl(reg); |
| |
| val |= bs; |
| writel(val, reg); |
| } |
| |
| static inline void sdr_clr_bits(void __iomem *reg, u32 bs) |
| { |
| u32 val = readl(reg); |
| |
| val &= ~bs; |
| writel(val, reg); |
| } |
| |
| static inline void sdr_set_field(void __iomem *reg, u32 field, u32 val) |
| { |
| unsigned int tv = readl(reg); |
| |
| tv &= ~field; |
| tv |= ((val) << (ffs((unsigned int)field) - 1)); |
| writel(tv, reg); |
| } |
| |
| static inline void sdr_get_field(void __iomem *reg, u32 field, u32 *val) |
| { |
| unsigned int tv = readl(reg); |
| *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); |
| } |
| |
| #endif |
