blob: 17020e24abd294055b321985c6806904eb1e8e81 [file] [log] [blame]
#include <dt-bindings/interrupt-controller/mips-gic.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mediatek,mt7621-soc";
cpus {
cpu@0 {
compatible = "mips,mips1004Kc";
};
cpu@1 {
compatible = "mips,mips1004Kc";
};
};
cpuintc: cpuintc@0 {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
aliases {
serial0 = &uartlite;
};
cpuclock: cpuclock@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
/* FIXME: there should be way to detect this */
clock-frequency = <880000000>;
};
sysclock: sysclock@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
/* This is normally 1/4 of cpuclock */
clock-frequency = <220000000>;
};
palmbus: palmbus@1E000000 {
compatible = "palmbus";
reg = <0x1E000000 0x100000>;
ranges = <0x0 0x1E000000 0x0FFFFF>;
#address-cells = <1>;
#size-cells = <1>;
sysc: sysc@0 {
compatible = "mtk,mt7621-sysc";
reg = <0x0 0x100>;
};
wdt: wdt@100 {
compatible = "mtk,mt7621-wdt";
reg = <0x100 0x100>;
};
gpio: gpio@600 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "mediatek,mt7621-gpio";
gpio-controller;
interrupt-controller;
reg = <0x600 0x100>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
};
i2c: i2c@900 {
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
clocks = <&sysclock>;
resets = <&rstctrl 16>;
reset-names = "i2c";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins>;
};
i2s: i2s@a00 {
compatible = "mediatek,mt7621-i2s";
reg = <0xa00 0x100>;
clocks = <&sysclock>;
resets = <&rstctrl 17>;
reset-names = "i2s";
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
txdma-req = <2>;
rxdma-req = <3>;
dmas = <&gdma 4>,
<&gdma 6>;
dma-names = "tx", "rx";
status = "disabled";
};
memc: memc@5000 {
compatible = "mtk,mt7621-memc";
reg = <0x300 0x100>;
};
cpc: cpc@1fbf0000 {
compatible = "mtk,mt7621-cpc";
reg = <0x1fbf0000 0x8000>;
};
mc: mc@1fbf8000 {
compatible = "mtk,mt7621-mc";
reg = <0x1fbf8000 0x8000>;
};
uartlite: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
clocks = <&sysclock>;
clock-frequency = <50000000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
no-loopback-test;
};
spi0: spi@b00 {
status = "disabled";
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
clocks = <&sysclock>;
resets = <&rstctrl 18>;
reset-names = "spi";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi_pins>;
};
gdma: gdma@2800 {
compatible = "ralink,rt3883-gdma";
reg = <0x2800 0x800>;
resets = <&rstctrl 14>;
reset-names = "dma";
interrupt-parent = <&gic>;
interrupts = <0 13 4>;
#dma-cells = <1>;
#dma-channels = <16>;
#dma-requests = <16>;
status = "disabled";
};
hsdma: hsdma@7000 {
compatible = "mediatek,mt7621-hsdma";
reg = <0x7000 0x1000>;
resets = <&rstctrl 5>;
reset-names = "hsdma";
interrupt-parent = <&gic>;
interrupts = <0 11 4>;
#dma-cells = <1>;
#dma-channels = <1>;
#dma-requests = <1>;
status = "disabled";
};
};
pinctrl: pinctrl {
compatible = "ralink,rt2880-pinmux";
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinctrl0 {
};
i2c_pins: i2c0 {
i2c0 {
groups = "i2c";
function = "i2c";
};
};
spi_pins: spi0 {
spi0 {
groups = "spi";
function = "spi";
};
};
uart1_pins: uart1 {
uart1 {
groups = "uart1";
function = "uart1";
};
};
uart2_pins: uart2 {
uart2 {
groups = "uart2";
function = "uart2";
};
};
uart3_pins: uart3 {
uart3 {
groups = "uart3";
function = "uart3";
};
};
rgmii1_pins: rgmii1 {
rgmii1 {
groups = "rgmii1";
function = "rgmii1";
};
};
rgmii2_pins: rgmii2 {
rgmii2 {
groups = "rgmii2";
function = "rgmii2";
};
};
mdio_pins: mdio0 {
mdio0 {
groups = "mdio";
function = "mdio";
};
};
pcie_pins: pcie0 {
pcie0 {
groups = "pcie";
function = "pcie rst";
};
};
nand_pins: nand0 {
spi-nand {
groups = "spi";
function = "nand1";
};
sdhci-nand {
groups = "sdhci";
function = "nand2";
};
};
sdhci_pins: sdhci0 {
sdhci0 {
groups = "sdhci";
function = "sdhci";
};
};
};
rstctrl: rstctrl {
compatible = "ralink,rt2880-reset";
#reset-cells = <1>;
};
clkctrl: clkctrl {
compatible = "ralink,rt2880-clock";
#clock-cells = <1>;
};
sdhci: sdhci@1E130000 {
status = "disabled";
compatible = "ralink,mt7620-sdhci";
reg = <0x1E130000 0x4000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
};
xhci: xhci@1E1C0000 {
status = "okay";
compatible = "mediatek,mt8173-xhci";
reg = <0x1e1c0000 0x1000
0x1e1d0700 0x0100>;
reg-names = "mac", "ippc";
clocks = <&sysclock>;
clock-names = "sys_ck";
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@1fbc0000 {
compatible = "mti,gic";
reg = <0x1fbc0000 0x2000>;
interrupt-controller;
#interrupt-cells = <3>;
mti,reserved-cpu-vectors = <7>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
clocks = <&cpuclock>;
};
};
nand: nand@1e003000 {
status = "disabled";
compatible = "mtk,mt7621-nand";
bank-width = <2>;
reg = <0x1e003000 0x800
0x1e003800 0x800>;
#address-cells = <1>;
#size-cells = <1>;
};
ethsys: syscon@1e000000 {
compatible = "mediatek,mt7621-ethsys",
"syscon";
reg = <0x1e000000 0x1000>;
#clock-cells = <1>;
};
ethernet: ethernet@1e100000 {
compatible = "mediatek,mt7621-eth";
reg = <0x1e100000 0x10000>;
clocks = <&sysclock>;
clock-names = "ethif";
#address-cells = <1>;
#size-cells = <0>;
resets = <&rstctrl 6 &rstctrl 23>;
reset-names = "fe", "eth";
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
mediatek,ethsys = <&ethsys>;
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
status = "off";
phy-mode = "rgmii";
phy-handle = <&phy5>;
};
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
phy5: ethernet-phy@5 {
reg = <5>;
phy-mode = "rgmii";
};
switch0: switch0@0 {
compatible = "mediatek,mt7621";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
mediatek,mcm;
resets = <&rstctrl 2>;
reset-names = "mcm";
ports {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
port@0 {
status = "off";
reg = <0>;
label = "lan0";
};
port@1 {
status = "off";
reg = <1>;
label = "lan1";
};
port@2 {
status = "off";
reg = <2>;
label = "lan2";
};
port@3 {
status = "off";
reg = <3>;
label = "lan3";
};
port@4 {
status = "off";
reg = <4>;
label = "lan4";
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
};
gsw: gsw@1e110000 {
compatible = "mediatek,mt7621-gsw";
reg = <0x1e110000 0x8000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
};
pcie: pcie@1e140000 {
compatible = "mediatek,mt7621-pci";
reg = <0x1e140000 0x100 /* host-pci bridge registers */
0x1e142000 0x100 /* pcie port 0 RC control registers */
0x1e143000 0x100 /* pcie port 1 RC control registers */
0x1e144000 0x100>; /* pcie port 2 RC control registers */
#address-cells = <3>;
#size-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
device_type = "pci";
bus-range = <0 255>;
ranges = <
0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xF0000 0 0 1>;
interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
<0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
<0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
resets = <&rstctrl 23 &rstctrl 24 &rstctrl 25 &rstctrl 26>;
reset-names = "pcie", "pcie0", "pcie1", "pcie2";
clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
clock-names = "pcie0", "pcie1", "pcie2";
phys = <&pcie0_port>, <&pcie1_port>, <&pcie2_port>;
phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
bus-range = <0x00 0xff>;
};
pcie@1,0 {
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
bus-range = <0x00 0xff>;
};
pcie@2,0 {
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
bus-range = <0x00 0xff>;
};
};
pcie0_phy: pcie-phy@1e149000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e149000 0x0700>;
#address-cells = <1>;
#size-cells = <0>;
pcie0_port: pcie-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
pcie1_port: pcie-phy@1 {
reg = <1>;
#phy-cells = <0>;
};
};
pcie1_phy: pcie-phy@1e14a000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e14a000 0x0700>;
#address-cells = <1>;
#size-cells = <0>;
pcie2_port: pcie-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
};
};