commit 24a01453892e0a4a6ad38460541bd0dae9b1837f
author Sergei Shtylyov <sshtylyov@ru.mvista.com> Tue Jan 30 20:40:30 2007 +0300
committer Jeff Garzik <jeff@garzik.org> Fri Feb 09 17:39:38 2007 -0500
tree bcf4e72523a229a67d12eb9798b40f975eeb04fc
parent 246ce3b675843e0369643cceb4faeb6cf6d19a30

pata_sl82c105: wrong assumptions about compatible PIO modes

Fix the wrong "compatible" PIO mode choices: MWDMA0 has 480 ns cycle while PIO1
only has 383 ns cycle, and MWDMA2 timings matchs those of PIO4 exactly.

Signed-off-by: Jeff Garzik <jeff@garzik.org>

drivers/ata/pata_sl82c105.c

diff --git a/drivers/ata/pata_sl82c105.c b/drivers/ata/pata_sl82c105.c
index a403456..f2fa158 100644
--- a/drivers/ata/pata_sl82c105.c
+++ b/drivers/ata/pata_sl82c105.c
@@ -139,13 +139,13 @@
 {
 	switch(adev->dma_mode) {
 		case XFER_MW_DMA_0:
-			sl82c105_configure_piomode(ap, adev, 1);
+			sl82c105_configure_piomode(ap, adev, 0);
 			break;
 		case XFER_MW_DMA_1:
 			sl82c105_configure_piomode(ap, adev, 3);
 			break;
 		case XFER_MW_DMA_2:
-			sl82c105_configure_piomode(ap, adev, 3);
+			sl82c105_configure_piomode(ap, adev, 4);
 			break;
 		default:
 			BUG();