)]}' { "commit": "02b4e2756e01c623cc4dbceae4b07be75252db5b", "tree": "2dfe7bc32d8ac07075eb6a3d057f92b15039932e", "parents": [ "6a53bc750004fdab11494e9e6c864b4a425fc1a1" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue May 19 17:06:44 2015 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jun 01 11:30:26 2015 +0100" }, "message": "ARM: v7 setup function should invalidate L1 cache\n\nAll ARMv5 and older CPUs invalidate their caches in the early assembly\nsetup function, prior to enabling the MMU. This is because the L1\ncache should not contain any data relevant to the execution of the\nkernel at this point; all data should have been flushed out to memory.\n\nThis requirement should also be true for ARMv6 and ARMv7 CPUs - indeed,\nthese typically do not search their caches when caching is disabled (as\nit needs to be when the MMU is disabled) so this change should be safe.\n\nARMv7 allows there to be CPUs which search their caches while caching is\ndisabled, and it\u0027s permitted that the cache is uninitialised at boot;\nfor these, the architecture reference manual requires that an\nimplementation specific code sequence is used immediately after reset\nto ensure that the cache is placed into a sane state. Such\nfunctionality is definitely outside the remit of the Linux kernel, and\nmust be done by the SoC\u0027s firmware before _any_ CPU gets to the Linux\nkernel.\n\nChanging the data cache clean+invalidate to a mere invalidate allows us\nto get rid of a lot of platform specific hacks around this issue for\ntheir secondary CPU bringup paths - some of which were buggy.\n\nReviewed-by: Florian Fainelli \u003cf.fainelli@gmail.com\u003e\nTested-by: Florian Fainelli \u003cf.fainelli@gmail.com\u003e\nTested-by: Heiko Stuebner \u003cheiko@sntech.de\u003e\nTested-by: Dinh Nguyen \u003cdinguyen@opensource.altera.com\u003e\nAcked-by: Sebastian Hesselbarth \u003csebastian.hesselbarth@gmail.com\u003e\nTested-by: Sebastian Hesselbarth \u003csebastian.hesselbarth@gmail.com\u003e\nAcked-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nTested-by: Thierry Reding \u003ctreding@nvidia.com\u003e\nAcked-by: Thierry Reding \u003ctreding@nvidia.com\u003e\nTested-by: Geert Uytterhoeven \u003cgeert+renesas@glider.be\u003e\nTested-by: Michal Simek \u003cmichal.simek@xilinx.com\u003e\nTested-by: Wei Xu \u003cxuwei5@hisilicon.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n", "tree_diff": [ { "type": "modify", "old_id": "4c38674c73ecb15d92702ca58b4d0f95bf2888fe", "old_mode": 33188, "old_path": "arch/arm/mach-bcm/Makefile", "new_id": "54d274da7ccba181c8ede133a6138c597ad3fa1a", "new_mode": 33188, "new_path": "arch/arm/mach-bcm/Makefile" }, { "type": "delete", "old_id": "ec0c3d112b367862e0f7127423328e2f0ebaed3e", "old_mode": 33188, "old_path": "arch/arm/mach-bcm/brcmstb.h", "new_id": "0000000000000000000000000000000000000000", "new_mode": 0, "new_path": "/dev/null" }, { "type": "delete", "old_id": "199c1ea582480062da9ad56c8996bfffe03c143c", "old_mode": 33188, "old_path": "arch/arm/mach-bcm/headsmp-brcmstb.S", "new_id": "0000000000000000000000000000000000000000", "new_mode": 0, "new_path": "/dev/null" }, { "type": "modify", "old_id": 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